Article ID: 000086179 Content Type: Product Information & Documentation Last Reviewed: 07/26/2018

How do I configure my SoC system for cache coherent accesses from the FPGA soft logic to the HPS memory?

Environment

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Description

To allow cache coherent accesses from FPGA soft logic to HPS memory number of items must be in place:

  • MMU page tables
  • NOC Security Settings
  • CoreLink™ Level 2 Cache Controller L2C-310 configuration
  • AXI sideband signals:  Axi_cache_security bridge 
    • AxCache and AxUser
    • AXPROT

MMU page tables

The MMU Page Tables must be set up so as to define the target memory area cacheable, and either secure, or  non secure.   See Linux and ARM documentation for more detail on MMU page table allocation attributes, and Secure Mode (trust zone).

  • The memory must be marked as Write back Write Allocate (WBWA). 
  • For memory to be accessed from a Linux user space application or Kernel the security mode should be non-secure.   
  • Secure should be used for memory to be accessed by a process running in the ARM secure state (not to be confused with supervisor mode).

Secure mode is enabled if CP15: SDR:NS = 1.   Note: the NS register will only be available in supervisor mode.

 

NOC Security Settings

The Arria® 10 SoC Network on Chip iinterconnect(NOC) is configurable with firewalls on each bridge and throughout the interconnect.   To allow accesses via the HPS bridges

  • The firewalls must be configured to allow transactions through the bridge
  • The master controls must be set to allow/disallow secure accesses
  • If a master is set to disallow secure accesses, all transaction will be changed to non-secure state, which can break coherency.

The U-boot generated from the SoC EDS software version 16.0 and later disables NOC firewalls, but sets master to disallow secure access.

To allow secure access via the FPGA2HPA bridge:

Set register fpga2soc_ctrl: allow_secure to 1 (default = 0,  don’t allow secure)

 

Level 2 Cache Controller configuration

CoreLink™ Level 2 Cache Controller L2C-310 configuration

It is recommended that the Aux Control register bit [22]: Shared attribute override enable bit is set to ON.    This setting disables optimizations in the L2 Cache controller which transform some non-cacheable accesses from the MPU cores or ACP port into Cacheable non-allocated accesses, and moves the point of coherency from the SDRAM to the L2 Cache.     The change in the point of coherency could cause problems if masters access the SDRAM via L3 or the FPGA2SDRAM bridge.

Reference: CoreLink™ Level 2 Cache Controller L2C-310, Revision: r3p3 Technical Reference Manual (ARM DDI 0246H (ID080112)): Section 2.3.2 Shareable attribute.  

The above is set by default in the latest u-boot-socfpga versions available from https://github.com/altera-opensource/u-boot-socfpga

 

Driving AXI sideband signals from Qsys: Axi_cache_security bridge 

The Axi_cache_security bridge should be used to drive AxCache/AxUser/AxProt sideband signals to the correct values.  The Axi_cache_security bridge can be found in the Arria 10 Bridge example https://www.altera.com/support/support-resources/design-examples.html

 

AxCache[3:0] sideband signals

The correct AxCache [3:0] setting is dependent on the MMU Page table settings

See ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition (ARM DDI 0406C.c (ID051414) ) : A3.5 Memory types and attributes and the memory order model AxCache[1] must be 1 for coherent accesses.

Reference: Cortex™-A9 MPCore® Revision: r3p0  Technical Reference Manual (ARM DDI 0407G (ID072711)): 2.4 Accelerator Coherency Port

AW(R)CACHE[3:0]

[3] -  Write allocable

[2] - Read allocable

[1] - Cacheable

[0] - Bufferable

Suggested initial value for AW(R)CACHE[3:0]

awcache = 0xF; // 4'b1111             Write Allocate, Read Allocate, Bufferable, Cacheable

arcache = 0xF; // 4'b1111              Write Allocate, Read Allocate, Bufferable, Cacheable

Note: These setting should be altered based on use case

 

AxUser[4-0] sideband signals

The AxUser signals are used to pass extra information, and for ACP transactions they are used to pass inner and outer cacheable information.

AW(R)User[3:0]

[0] -  shared attribute must be set to 1 for coherent accesses 

[3:1] - Not interpreted by the SCU as the ACP has no inner cache policy, and are passed to the L2 Cache Controller for use if the cache is setup in exclusive mode.

               References: Cortex™-A9 MPCore® Revision: r3p0 Technical Reference Manual (ARM DDI 0407G (ID072711)): 2.4 Accelerator Coherency Port,  

Suggested initial value for AxUSER[4:0]

awuser  = 0x1; // 5'b00001

aruser  = 0x1; // 5'b00001

Note:  On Arria 10, the AXI shared attribute is internally tied to “1” . 

 

AxProt[2:0] sideband signals

AxProt specifies the secure state of the transaction, and must match the security state of the target memory to ensure a cache hit.  

AW(R)PROT[2:0]

[2] - instruction fetch

[1] - non-secure access

[0] - privileged access

 

Suggested initial value for AxProt[2:0]

MMU page table memory security setting, and CPU secure setting and ACP transaction secure state must all match to ensure cache hit. 

A non-secure ACP transaction to a secure memory location accessed by a CPU in secure state will result in a cache miss, and an in-coherent access.

 

 

Summary of supported scenarios:

Non-Secure

  • The MMU Page Table is set up to define the target memory area as non secure
  • The NOC firewalls are set up so as to allow non secure access to the target area
  • The F2H bridge performs secure or non-secure accesses to the target area

Secure

  • The MMU Page Table is set up to define the target memory area as secure
  • The NOC firewalls are set up to allow secure access to the target area
  • The F2H bridge performs a secure access to the target area.

Related Products

This article applies to 1 products

Intel® Arria® 10 SX SoC FPGA

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