When using the Nios II® Gen2 core, the peripheral region is introduced, where there is a 32-bit address option. With Nios II® Gen2, for an uncached write, where bit 31 is set or in the peripheral memory region, the cache is bypassed.
Uncached data and cached data can no longer be allocated on the same line in the data cache, because Nios II® Gen2 core does not update the cache in an uncached line. This is the behavior for Nios II® Classic. However, NIOS II® gen2 is no longer updates the cache for uncached writes.
If you have existing Nios II® code and use a Nios II/f® Gen2 with a data cache, then you have to check your software to ensure that it does not mix cacheable and uncacheable data on the same cache line.
Once you are done with writing your data, you should make sure to flush the cache by using function alt_dcache_flush(void* start, alt_u32 len). This function flushes the data cache for a memory region of length len bytes, starting at address start. Flushing the cache consists of writing back dirty data and then invalidating the cache.