Article ID: 000086115 Content Type: Troubleshooting Last Reviewed: 11/18/2011

Erroneous Timing Failures in Designs Containing Both UniPHY and ALTMEMPHY Instantiations for External Memory Interfaces

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    Designs containing both UniPHY and ALTMEMPHY instantiations may encounter erroneous clock failures during timing analysis.

    Resolution

    The workaround for this issue is to open the UniPHY <core_name>_report_timing.tcl and <core_name>_pin_map.tcl files in an editor, and make the following change in each file:Locate the traverse_to_ddio_out_pll_clock function name, and append the numeral 2 to the function name, making it traverse_to_ddio_out_pll_clock2.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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