The following list the sequence of events why you experience Nios® II processor system lockup when accessing the Generic Tri-state Controller IP with waitrequest signal enabled:
- When waitrequest signal is enabled, the Read wait time/Write wait time/Setup time/Data hold time must be set to zero. Enabling waitrequest signal with a non-zero value on the wait, setup, and hold time is an illegal parameterization.
- However, due to a limitation in the system, the Platform Designer does not validate this illegal setting and prompts an error to warn the user.
- Because of the illegal settings, an internal component in the controller is parameterized incorrectly, which causes the IP to gate the read/write request signal. The IP will only assert request to the pin sharer when waitrequest signal is high.
To avoid this error, in the Generic Tri-State Controller IP GUI, make sure that the Read wait time/Write wait time/Setup time/Data hold time in the Signal Timing tab is set to zero when waitrequest signal is enabled in the Signal Selection tab.
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Alternately if the settings above is not met, you can also avoid system lockup by keeping waitrequest high during idle states/no transactions. A high waitrequest during idle cycles allows request to be asserted to the pin sharer and normal operation to continue. However, this is not recommended unless you are not able to follow the workaround stated above.