Article ID: 000086053 Content Type: Error Messages Last Reviewed: 08/04/2023

Internal Error: Sub-system: SIN, File: /quartus/h/sin_micro_tnodes_enum_translator_auto.cpp. Line: 5985

Environment

  • Quartus® II Software
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Quartus® II software version 13.0sp1, you may see this internal error when running the PowerPlay Power Analyzer if a transceiver receiver channel uses either the LVDS or the Differential LVPECL I/O standard, targeting Cyclone® V, Arria® V, and Stratix® V devices.

     

    The power analyzer misidentifies transceiver channels as general-purpose I/O (GPIO) pins, but the GPIO pins do not have data on HSSI-specific termination settings.

     

    Resolution

    A patch is available to fix this for the Quartus® II software version 13.0sp1.

    This patch allows the power analyzer to correctly identify transceiver channels and retrieve the appropriate data for its calculations.

     

    This problem is fixed in Intel® Quartus® 13.1.

    Related Products

    This article applies to 15 products

    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA

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