When there is one or more corner PLLs used to drive the LVDS transmitter and/or receiver channels, the LOADEN signal to the LVDS SERDES may be incorrectly connected in certain Quartus® II software fitter seeds. This causes the SERDES to shift out the incorrect data pattern and causes data errors to the LVDS interface. This issue will not occur if only a center PLL is used.
This issue only affects Stratix® III, Stratix IV (GX, GT, E), Arria® II (GX, GZ), HardCopy® III, and HardCopy IV (GX, E) device families. Other device families are not affected.
To identify whether corner or center PLL is used in your design, you can view the “PLL summary” section in the Quartus II software fitter report and refer to the Clock networks and PLLs chapter in the respective device handbook:
If your ALTLVDS design is using corner PLLs but you do not encounter any LVDS data error issue in the existing design, this implies the Quartus II software has chosen the pass fitter seeds for the compilation and therefore no action is required. If a design is working it will consistently pass in the future unless there is a recompilation attempt prior to the Quartus II software version 11.1. To reduce the potential risk to the ALTLVDS design during recompilation, you are recommended to apply the software patch when you recompile your design in the Quartus II software prior to version 11.1, or recompile your design in the Quartus II software version 11.1 which has the software fix implemented.
This problem can be fixed by applying the software patches below and recompile the design. If you need software patches for a Quartus II software version prior to 10.1, please contact mySupport for further assistance.
For Quartus II version 10.1:
For Quartus II version 10.1SP1:
For Quartus II version 11.0:
For Quartus II version 11.0SP1:
This issue is fixed in the Quartus II software version 11.1.