Article ID: 000086038 Content Type: Product Information & Documentation Last Reviewed: 02/13/2006

How do I use all of the available clocking resources in Stratix™ devices with the Quartus® II software version 2.0?

Environment

  • Clock
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Stratix devices have 24 clock pins: 16 dedicated clock pins that can either drive global or regional clock networks and 8 fast regional FCLK pins that can drive fast regional clock networks.

    Because you cannot access all of the clocking resources through the pins, you have to use the dedicated pins together with phase-locked loop (PLL) outputs and internal logic routed to global resources to use all the clock networks in the device. Table 1 lists the global clock inputs.

    Table 1. Stratix Clock Inputs
    ClockInput
    16 dedicated global clocks
    • Dedicated clock pins
    • Internal logic
    • PLL outputs
    16 regional clocks
    • Dedicated clock pins
    • PLL outputs
    8 fast regional clocks
    • Fast regional clock pins

    Use the Assignment Organizer in the Quartus II software to make regional and fast regional clock assignments because there is no HDL primitive available for them. Use the GLOBAL primitive to make dedicated global clock assignments (you can also use the Assignment Organizer in the Quartus II software). See Quartus II On-Line Help for more information on the GLOBAL primitive. See the Stratix Device Family Data Sheet in the Stratix Device Handbook for more information on the global routing structure in Stratix devices.

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    Intel® Programmable Devices

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