Due to a problem in the Quartus® II software version 11.1 SP2 and earlier, the write_sdc command may generate incorrect Synopsys Design Constraints (SDC) syntax for create_generated_clock constraints which use the -edges option. In particular, the write_sdc command may generate SDC syntax with extra braces "{}" around the -edges argument and insert an additional -edge_shift option.
For example, if this constraint were applied to the design:
create_generated_clock -name CLK2 -source [get_pins {inst10|clk}] -edges {31 33 63}
[get_pins {inst10|regout}]The write_sdc command may write out the following constraint instead:
create_generated_clock -name {CLK2} -source [get_pins {inst10|clk}]
-edges { { 31 33 63 } } -edge_shift {} -master_clock {CLK1}
[get_pins {inst10|regout}]To work around this problem, manually edit the SDC file created by the write_sdc command, remove the extra braces around the -edges argument and remove the -edge_shift option and its argument.
This problem is fixed beginning with the Quartus II software version 12.0.