Article ID: 000086008 Content Type: Troubleshooting Last Reviewed: 07/22/2020

Why EMAC0 of Cyclone® V SOC HPS is not counting packets like EMAC1 ?

Environment

  • Intel® Quartus® Prime Lite Edition
  • Intel® Quartus® Prime Standard Edition
  • Arria® V Cyclone® V Hard Processor System Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Cyclone® V SoC HPS, EMAC0 is not constantly counting the incoming packets as EMAC1 do. Some packets might be lost in counting, however, they have been received by the system.

    Resolution

    To work around this problem in the Cyclone® V SoC HPS EMAC0, you need to follow the steps below:

    1- Operate the RxFIFO in the store-and-forward mode.

    2- Operation_Mode Register: located at address:

    0xFF701018 (for EMAC0)

    0xFF703018 (for EMAC1)

    Set bit 25 (“rsf” bit) to 0x1

    Related Products

    This article applies to 3 products

    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V SE SoC FPGA

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