Article ID: 000086007 Content Type: Troubleshooting Last Reviewed: 04/13/2021

Why Arria® 10 SGMII Reference design in rocketboards.org doesn't work property?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HPS GMII to RGMII Converter Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software versions, you might see any errors with Arria® 10 SGMII Reference design on Arria® 10 SoC.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition software version 20.3 or later, follow the steps below

    1) Open attached script (run-cal-slack.tcl)

    2) Edit instance name for GMII to SGMII converter in the run_cal_slack.tcl as below

           set EMAC0   sgmii_1

           set EMAC1    sgmii_2

           set EMAC2    null

           set EMAC3    null

    The script can support up to 4 ports. A variable should be set ‘null’ if not needed.

    3)    Launch Timing Analyzer

    4)    Run updated script from a menu ( Script > Run Tcl Script )

    5)    End of the workaround if the script returns 0.

    6)    Add two constraints below to top sdc in your project such as ghrd_timing.sdc.

         set_net_delay -min 1.2 -from [get_registers {*|altera_gts_clock_gate:u_pcs_tx_clk_gated|en_flp}] -to [get_pins -compatibility_mode {*|u_pcs_tx_clk_gated|clk_gated|combout}]

         set_net_delay -min 1.2 -from [get_registers {*|altera_gts_clock_gate:u_pcs_rx_clk_gated|en_flp}] -to [get_pins -compatibility_mode {*|u_pcs_rx_clk_gated|clk_gated|combout}]

    7)    Recompile your design.

    8)    Go to 3 if a timing is met. 

    This problem is currently scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 SX SoC FPGA

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