Article ID: 000085998 Content Type: Error Messages Last Reviewed: 05/18/2021

Internal Error: Sub-system: LVDS, File: /quartus/periph/lvds/lvds_gen6.cpp, Line: 787

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, you may see the internal error above at Fitter stage when there is a PLL connected to multiple LVDS IPs with outclk channel in the same IO bank. This problem only affects Intel® Arria® 10 devices.

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 21.1.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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