Article ID: 000085987 Content Type: Troubleshooting Last Reviewed: 08/13/2012

If I remove the input clock to my PLL in Stratix series and Cyclone series devices whilst in user mode, what is the behaviour of the PLL output clock(s)?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

If you remove the input clock to a PLL in a Stratix® - series, Cyclone® - series, or Arria®  GX device, the VCO will drift to an unspecified floor frequency. The PLL output clock(s) is then equal to the unspecified VCO floor frequency divided by the output counters for the PLL clock output(s).

Note that the VCO floor frequency can vary from device to device due to process variation.

Related Products

This article applies to 9 products

Cyclone® III FPGAs
Cyclone® II FPGA
Stratix® FPGAs
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Cyclone® FPGAs
Stratix® IV GX FPGA
Stratix® III FPGAs

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