Avalon® Memory Mapped accesses to the transceiver reconfiguration controller in the Arria® V, Cyclone® V, and Stratix® V, devices will hang if the accesses are made to addresses outside of the specified address space of Table 16-8 of the Altera Transceiver Phy IP Core User Guide.
Article ID: 000085985 Content Type: Troubleshooting Last Reviewed: 06/29/2014
Why does my Avalon Memory Mapped bus hang when accessing the transceiver reconfiguration controller in Arria V, Cyclone V and Stratix V devices?
BUILT IN - ARTICLE INTRO SECOND COMPONENT
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