Article ID: 000085985 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Why does my Avalon Memory Mapped bus hang when accessing the transceiver reconfiguration controller in Arria V, Cyclone V and Stratix V devices?

Environment

  • Cyclone® V SX SoC FPGA
  • Cyclone® V GT FPGA
  • Stratix® V GX FPGA
  • Cyclone® V GX FPGA
  • Stratix® V GT FPGA
  • Stratix® V GS FPGA
  • Arria® V GZ FPGA
  • Arria® V SX SoC FPGA
  • Cyclone® V ST SoC FPGA
  • Arria® V ST SoC FPGA
  • Arria® V GX FPGA
  • Arria® V GT FPGA
  • Cyclone® V E FPGA
  • Stratix® V E FPGA
  • Cyclone® V SE SoC FPGA
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Description

Avalon® Memory Mapped accesses to the transceiver reconfiguration controller in the Arria® V, Cyclone® V, and Stratix® V, devices will hang if the accesses are made to addresses outside of the specified address space of Table 16-8 of the Altera Transceiver Phy IP Core User Guide.

http://www.altera.com/literature/ug/xcvr_user_guide.pdf

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