Article ID: 000085976 Content Type: Troubleshooting Last Reviewed: 02/13/2006

Can the Stratix™ enhanced phase-locked loop's (PLL's) automatic clock switchover circuitry be dynamically enabled or disabled?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description No. The enhanced PLL does not have a dynamic enable or disable control port for just the automatic clock switchover circuitry; you cannot manually control whether automatic switchover was on or off. You must program the PLL with automatic switchover either enabled or disabled.

    You can enable the clock sense circuitry but not enable the automatic switchover feature. By enabling the clock sense circuitry, two PLL output ports, CLKBAD0 and CLKBAD1, are enabled. These ports indicate whether the primary or secondary clocks have stopped running. Then, using custom-designed logic, you can manually toggle the CLKSWITCH control port to decide whether the PLL switches from primary to secondary or back.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs

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