Article ID: 000085960 Content Type: Troubleshooting Last Reviewed: 09/24/2018

Qsys interconnect wait for WLAST might deadlock some AXI masters

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
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Critical Issue

Description

The master-side of the Qsys interconnect waits for a WLAST signal before it asserts an AWREADY signal to minimize area. This might cause deadlock for some AXI masters.

Resolution

Insert a pipelined AXI bridge between the master and the interconnect

Related Products

This article applies to 1 products

Intel® Programmable Devices

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