Article ID: 000085932 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: Clock output port of fast or enhanced PLL has illegal Global Signal option setting Off -- must be set to Global Clock or Regional Clock



This error may occur in a bottom-up incremental compilation flow when a PLL uses a different type of clock resource in a lower-level design partition than in the top-level design. For example, the error may occur if a PLL has a dedicated connection from the device clock pin to the PLL input clock in the lower-level design, but the PLL clock input is fed by a different type of clock source (such as a global routing resource) in the top-level design. When you import the lower-level design into the top level, the new clock resource cannot connect to the PLL clock input in the partition, because it does not use the same type of clock resource.

To override the type of routing resource used in this example, explicitly apply a GLOBAL_SIGNAL assignment to the PLL clock input in the lower-level design before you compile and export the partition, as follows:

set_instance_assignment -name GLOBAL_SIGNAL ON -to "<PLL clock input>"



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Stratix® II FPGAs



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