Article ID: 000085928 Content Type: Troubleshooting Last Reviewed: 11/08/2015

Unable to Generate JESD204B IP Core Design Example in Qsys due to IP Connectivity Errors

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When you first instantiate the JESD204B IP core in a Qsys project, the Messages panel displays connectivity errors because the ports have not yet been connected. These errors indicate system-level connectivity errors and prevents you from generating a JESD204B IP core design example. When you open the IP parameter editor and click \'Generate Example Design\' with the connectivity errors still present, you will get the following error message:

The example design cannot be generated when there are errors.

Resolution

Set all the necessary interconnects in your Qsys project to eliminate the connectivity errors. You will then be able to generate the design example.

Alternatively, instantiate the IP core from the IP Catalog to avoid this error.

For a more detailed instruction to instantiate the IP core from the IP Catalog and generate the design example, follow the steps in Chapter 5: JESD204B IP Core Design Examples > Selecting and Generating the Design Example of the JESD204B IP Core User Guide.

This issue will be fixed in a future release.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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