Article ID: 000085890 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does changing the board_skew parameter in my sdc file not affect my read capture and write timing margins for DDR, DDR2, DDR3 High Performance Controller or Altmemphy Megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Changing the board skew number merely in sdc file does not change the read capture and write margin. You need to change the board skew value in the <varition_name>_report_timing.tcl file for the skew number to get accounted for in the margins computation.

Altera uses macro timing methodology to compute read capture, write margins.  These numbers are computed by substituting memory preset values, board skew value, and characterized tccs, tsw values in the read and write capture equations as written in the <variation_name>_report_timing.tcl file.  To report DDR timing margins Quartus® II software sources this tcl file. Refer to AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices (PDF) for more details on timing analysis.

You should always regenerate the DDR, DDR2, DDR3 High Performance Controller core and Altmemphy Megafunction with new skew numbers to perform timing analysis with the updated skew numbers.

Related Products

This article applies to 6 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA
Cyclone® III FPGAs
Stratix® III FPGAs
Arria® II GX FPGA

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