Article ID: 000085885 Content Type: Troubleshooting Last Reviewed: 01/12/2023

Why is the data out of my RAM delayed by an extra clock cycle?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1, you may see the data out of your RAM is delayed by a clock cycle. This problem occurs when the RAM block type is set to AUTO, the Clock Enable is connected, and the RAM has been implemented as an MLAB. This problem only affects Intel® Stratix® 10 devices.

    Resolution

    To work around this problem, set the RAM block type to M20K or do not connect the Clock Enable.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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