Description
Due to a problem with MAX® 10 Modular ADC IP VHDL simulation setup, incorrect models are generated.
This error message is issued when VHDL simulation is started, it occurs due to an incorrect module name being used in automatically generated VHDL simulation models.
Resolution
To work around this problem, use the Verilog HDL simulation model.
VHDL simulation is not supported for the MAX 10 Modular ADC IP.
