Article ID: 000085867 Content Type: Error Messages Last Reviewed: 07/18/2017

Error: (vsim-3033) ./../submodules/_modular_adc_0.v(26): Instantiation of '_modular_adc_0_control_internal' failed. The design unit was not found.

Environment

  • Intel® Quartus® Prime Pro Edition
  • Modular ADC core Intel® FPGA IP
  • Modular Dual ADC core Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with MAX® 10 Modular ADC IP VHDL simulation setup, incorrect models are generated.

    This error message is issued when VHDL simulation is started, it occurs due to an incorrect module name being used in automatically generated VHDL simulation models.  

    Resolution

    To work around this problem, use the Verilog HDL simulation model.

    VHDL simulation is not supported for the MAX 10 Modular ADC IP.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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