Article ID: 000085863 Content Type: Troubleshooting Last Reviewed: 12/05/2014

Why do I get a no-fit when using the Altera External Memory Interface IP in an FPGA device that has a relatively low number of IO banks?

Environment

    Quartus® II Subscription Edition
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Description

When compiling the DDR3, DDR2, LPDDR2, QDRII or RLDRAM II Controller with UniPHY IP using an FPGA device that has relatively low number of IO banks, you may experience a no-fit and possibly the following Quartus® II error. 

Error (175020): Illegal constraint of fractional PLL to the region

The problem occurs if all the IO banks on a certain side of the FPGA have been fully used by the memory interface and the PLL input reference clock and other miscellaneous memory interface pins do not have the same IO standard as the memory interface IO.

Resolution

Set the PLL input reference clock and other miscellaneous memory interface pins to have same IO standard as the memory interface IO.

Related Products

This article applies to 19 products

Cyclone® V SX SoC FPGA
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Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
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Stratix® III FPGAs
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
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Cyclone® V SE SoC FPGA

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