Altera Recommends Not Using afi_half_clk

This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products.

The following warning messages may be displayed in the TimeQuest Timing Analyzer after running the Report DDR command.

On Arria V devices with DDR2, DDR3, LPDDR2, QDR II, or RLDRAM II interfaces:

Timing analysis was performed on core <corename> using Quartus II v12.0 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

On Arria V devices with LPDDR2, QDR II, or RLDRAM II interfaces:

Core: <corename> was generated using Quartus II v12.0 for Arria V. POF generation is not supported for this core in this release of Quartus II. You must regenerate this IP in a future version of Quartus II to obtain POF support..

On Cyclone V devices with DDR2, DDR3, or LPDDR2 interfaces:

Core: <corename> was generated using Quartus II v12.0 for Cyclone V. POF generation is not supported for this core in this release of Quartus II. You must regenerate this IP in a future version of Quartus II to obtain POF support. Timing analysis was not performed on core <corename> because the Quartus II v12.0 software contains preliminary timing models for Cyclone V devices. You must regenerate this IP in a future version of Quartus II to update the timing model and constraints.

On Stratix V devices with DDR2, DDR3, QDR II, or RLDRAM II interfaces:

Timing analysis was performed on core <corename> using Quartus II v12.0 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

The workaround for this issue is to not use afi_half_clk.

This issue will not be fixed.