Article ID: 000085853 Content Type: Troubleshooting Last Reviewed: 12/26/2014

Faulty Progressive Input Placement

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

When you provide external synchronization signals to the Clocked Video Input II IP core and configure it to use interlaced video by turning on the Extract Field signal parameter, you must set the Field order parameter to either Any field first or Field 0 first. When you do this, the progressive input will incorrectly place its vertical field parameters in the F1 registers.

Resolution

To work around this issue, when you enable the Extract Field signal parameter, read the F1 registers for progressive height instead of the F0 registers.

This issue is fixed in version 14.1 of the Clocked Video Input II IP core.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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