Article ID: 000085820 Content Type: Product Information & Documentation Last Reviewed: 09/05/2012

How do I regenerate a functional simulation model for a SerialLite II variant after I have edited the MegaWizard generated HDL files?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This solution guides you through the process of generating a new functional simulation model for a SerialLite®  II variant after you have made modifications to any of the MegaWizard® GUI generated files.

Open a new file and name it "create_new_simgen.bat". This will be an ms-dos executable file. Similarly, a Unix based script (e.g. bash) can be created.

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For Verilog: Add the following text to the file, replacing <v_n> with your variation name (the name used in the MegaWizard).  Make sure that the text is all within one line.

quartus_map <v_n>_slite2_top --family="stratixiigx" --simgen
--simgen_parameter="CBX_HDL_LANGUAGE=verilog, CBX_FILE=<v_n>_slite2_top.vo"
--source=<v_n>_rxhpp_atlfifo_concat.v --source=<v_n>_rxrdp_atlfifo_concat.v
--source=<v_n>_slite2_top.v --source=<v_n>_slite2_unenc.v
--source=<v_n>_slite2_wrapper.v --source=<v_n>_txhpp_atlfifo_concat.v
--source=<v_n>_txrdp_atlfifo_concat.v

Save the file and exit the text editor.

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For VHDL: Add the following text to the file, replacing <v_n> with your variation name (the name used in the MegaWizard).  Make sure that the text is all within one line.

quartus_map <v_n>_slite2_top --family="stratixiigx" --simgen
--simgen_parameter="CBX_HDL_LANGUAGE=vhdl, CBX_FILE=<v_n>_slite2_top.vho"
--source=<v_n>_rxhpp_atlfifo_concat.v --source=<v_n>_rxrdp_atlfifo_concat.v
--source=<v_n>_slite2_core.v --source=<v_n>_slite2_top.v
--source=<v_n>_slite2_unenc.v --source=<v_n>_slite2_wrapper.v
--source=<v_n>_txhpp_atlfifo_concat.v --source=<v_n>_txrdp_atlfifo_concat.v

Save the file and exit the text editor.

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Notes:

1.      This example is targeting a Stratix® II GX device.  If you are targeting a different family please make that modification to the file by changing the --family field from “stratixiigx” to your device family.

2.      Not all the files shown may be present in your directory (For example, if your SerialLite-II MegaCore® function was configured in streaming mode, the files <v_n>_txhpp_atlfifo_concat.v, <v_n>_rxhpp_atlfifo_concat.v, <v_n>_txrdp_atlfifo_concat.v, <v_n>_rxrdp_atlfifo_concat.v, and <v_n>_slite2_core.v are not present, and do not need to be included in the quartus_map command shown above. Ensure the file exists before adding to the quartus_map command.

Now execute "create_new_simgen.bat" in an ms-dos command shell or double-click on the file.  You should now have a new functional simulation model (.vo or .vho) file that reflects the modifications that you made to the "<vn>_slite2_wrapper.v" file.

Related Products

This article applies to 2 products

Stratix® GX FPGA
Stratix® II GX FPGA

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