You will get this error message when trying to generate a simulation file from Qsys that includes a PCIe® Hard IP for Cyclone® IV devices being called from 64-bit Quartus® II software in Linux.
Info: altgx_internal: qmegawiz -silent module=alt_c3gxb LOCKDOWN_EXCL=PCIE IP_MODE=PCIE_HIP_8 gxb_analog_power=AUTO tx_analog_power=AUTO elec_idle_infer_enable=false tx_allow_polarity_inversion=false rx_cdrctrl_enable=true hip_tx_clkout rx_elecidleinfersel fixedclk enable_0ppm=false pll_powerdown intended_device_family=cycloneiv starting_channel_number=84 deviceFamily="Cyclone IV GX" wiz_subprotocol="Gen 1-x1" OPTIONAL_FILES=NONE mi_pcie_pcie_hard_ip_0_altgx_internal_inst.v
Info: altgx_internal: Generating Verilog simulation model
Error: Node "<path>:altgx_internal|alt_c3gxb:alt_c3gxb_component|alt_c3gxb_qbn8:auto_generated|refclk_pma[0]" is missing source File: <path>/alt_c3gxb_qbn8.tdf Line: 311
From a command line (terminal), append QUARTUS_ROOTDIR to the PATH of your environment variable and then open Qsys from the command line (terminal).To implement this, run the following two commands from the command prompt:
export PATH=/bin:/build2/install/mongodb/bin:/usr/lib64/qt-3.3/bin:/usr/NX/bin:/usr/local/bin:/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/jchang/bin
qsys-edit
The GUI will appear and once the project is opened, click generate.