Why do I get Error 11128 when compiling my Quartus project that instantiates a Qsys system with the HPS component?

When instantiating the HPS component in a top level verilog or VHDL design file if the port list is not identical to the Qsys generated port list you will see this error. The error will not report the exact signal causing the error. It will report the last signal in the instantiated port list. To ensure accuracy when instantiating the Qsys system, cut and paste the instantiation example in the Qsys "HDL Example" tab into the top level wrapper file.

This is an example of the complete error message:

Error (11128): The following signal cannot be routed: soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0].  The device does not contain the routing resources required to make this connection.