Why is my VHDL for loop not synthesized correctly?

Due to a problem in the Quartus® II software versions 12.0 and later, you may not get a warning or error that the right bound of range must be constant when you have the following VHDL construct:

for J in 0 to <variable> loop
 <code>
end loop;

This VHDL construct is not supported by Quartus II Integrated Synthesis and may result in incorrect synthesized logic.

To avoid this problem, do not use this construct even though the Quartus II software does not give a warning or error.

This construct generates an appropriate message beginning with the Quartus II software version 12.1 SP1.