Article ID: 000085771 Content Type: Troubleshooting Last Reviewed: 12/20/2012

Transceiver Reconfiguration Controller IP Core fail min pulse width on av_reconfig_pma_testbus_clk signal

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description This is a known issue and it will be fix in future Quartus® II release.
    Resolution

    Create an external SDC constraint with this constraint and recompile Quartus II project:

    create_generated_clock -name {av_reconfig_pma_testbus_clk}
    -source [get_pins -compatibility_mode {*|basic|a5|reg_init[0]|clk}]
    -divide_by 2 [get_registers {*av_xcvr_reconfig_basic:a5|*alt_xcvr_arbiter:pif*|*grant*}]

    Related Products

    This article applies to 1 products

    Cyclone® V GT FPGA

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