The I/O timing, which includes Address/Command, DQS gating, Read capture, Write and Write Levelling, is fully calibrated over process, voltage and temperature (PVT), and therefore, the margins are the same across all models. TimeQuest Report DDR reports the worst case values over all corners for these calibrated interfaces.
Article ID: 000085752 Content Type: Troubleshooting Last Reviewed: 08/25/2015
Why are the timing margins the same values for all corners when performing Report DDR in TimeQuest for Arria 10 external memory interfaces?
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