Article ID: 000085752 Content Type: Troubleshooting Last Reviewed: 08/25/2015

Why are the timing margins the same values for all corners when performing Report DDR in TimeQuest for Arria 10 external memory interfaces?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The I/O timing, which includes Address/Command, DQS gating, Read capture, Write and Write Levelling, is fully calibrated over process, voltage and temperature (PVT), and therefore, the margins are the same across all models. TimeQuest Report DDR reports the worst case values over all corners for these calibrated interfaces.

Related Products

This article applies to 3 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA

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