Article ID: 000085743 Content Type: Troubleshooting Last Reviewed: 12/01/2015

New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP

Environment

  • Intel® Quartus® Prime Pro Edition
  • I O
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In version 15.1, the valid range of selectable PLL Reference Clock Frequency values is reduced.

    • For VCO frequencies below 400 MHz, the value of the PLL M counter must now be within the range of 2 to 7, inclusive.
    • For VCO frequencies between 400 MHz and 600 MHz, the value of the PLL M counter must be within the range of 2 to 15, inclusive.
    • For VCO frequencies equal to or greater than 600 MHz, the value of the PLL M counter must be greater than or equal to 4.

    Users with designs parameterized on an earlier version may encounter errors when generating their EMIF IP in version 15.1.

    Resolution

    There is no workaround for this issue.

    This issue will not be fixed.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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