Gate Level Simulation Fails

Gate level simulation of the example design and example testbench fails when Use differential DQS is enabled in the DDR2 High-Performance Controller.

This issue affects DDR2 SDRAM High-Performance Controller designs in Stratix III and Stratix IV devices that have the Use differential DQS option enabled.

Gate level simulation of the example design does not behave correctly.

Altera recommends that you validate the functional operation of your design via RTL simulation, and the timing of your design using TimeQuest Timing Analysis.