Article ID: 000085715 Content Type: Troubleshooting Last Reviewed: 02/08/2013

Rounding error might cause clock edge misalignment in timing analysis

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    If you use the TimeQuest Timing Analyzer to analyze a design that contains a noninteger phase shift relationship between the launch clock and the latch clock, timing analysis might fail. Rounding errors that occur during timing analysis cause periodic clock edge misalignments.

    Resolution

    Avoid specifying a phase shift that is not integrally divisible by the clock period.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices