You may experience data corruption using any of the DDR (1/2/3) SDRAM controllers in Altera® SOPC Builder. This is caused by the burst line wrapping used by the SDRAM controller and the SOPC Builder burst adapters failing to adapt the SDRAM controller slave port to a sequential bursting master port. The burst boundary of any slave port can be determined using the following formula:
Slave burst boundary size [bytes] = Slave data width [bytes] * Slave maximum burst length [beats]
For example, if you use the DDR SDRAM controller for a x16 burst length of 4 device, the burst boundary size is 8 bytes. As a result, if a sequential burst master initiates a burst read or write transaction to the memory without starting on an 8 byte boundary, data corruption will occur. If the master posts a 2 beat burst transaction to byte address 4 of this memory, it will access bytes 4-7 during the first beat, and bytes 0-3 on the second beat (instead of addresses 8-11).
To avoid this data corruption you can use the following:
- Always align transfers to burst boundaries of the slave port using the formula above.
- Architect your master to post bursts of 1 beat until the next master burst boundary is reached.
- Disable burst support of your master or slave, in the case of the high performance DDR SDRAM controllers you can also use half-rate mode to avoid burst support.