Article ID: 000085694 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any known issues with "Non-Leveling" UniPHY based DDR3 SDRAM Controller in Quartus II software versions 10.0 and 10.0SP1?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes. When your design instantiates "Non-Leveling" DDR3 SDRAM Controller with UniPHY in the Quartus® II software version 10.0 and 10.0 SP1, you may see the following warnings during compilation.

Warning: Ignored filter at <IP core name>.sdc(500): *aligned_oe* could not be matched with a clock or keeper or register or port or pin or cell or partition
Warning: Ignored set_false_path at <IP core name>.sdc(500): Argument <from> is not an object ID
 Info: set_false_path -from *aligned_oe* -to

As a result, the timing margin report is imcomplete. You may find only Write timing margin report generated in "Report DDR".

To work around this problem, please use "Autoleveling selection" mode.

This issue has been fixed in Quartus II software version 10.1 and above.

 

Related Products

This article applies to 1 products

Stratix® IV GX FPGA

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