No, mixed-width implementations are not supported for MLABs.
Page 4-6 of the Stratix® III Device Handbook incorrectly states that MLABs can support mixed data widths through emulation via the Quartus II software. Also on page 4-10, it incorrectly states that the Quartus® II software can implement mixed width memories in MLABs by using more than one MLAB.
If you generate a mixed-width FIFO in MLABs, the following error message will be generated:
Error: Cannot use Write port width with Read port width in DCFIFO megafunction. The width ratio should be a power of 2.
Error: Assertion error: Valid clear box generator not found or Errors encountered during clear box generation
Error: Can't elaborate user hierarchy <component hierarchy>
This problem is scheduled to be fixed in a future version of the documentation.