Article ID: 000085672 Content Type: Troubleshooting Last Reviewed: 01/29/2015

Verilog HDL simulation model for ALTERA_FP_MATRIX_MULT IP core produces incorrect simulations

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Because of a problem with the Verilog HDL simulation model for the ALTERA_FP_MATRIX_MULT IP core, the simulation output is incorrect. This problem affects the NCSim software only.

Resolution

Use the VHDL simulation model

Related Products

This article applies to 1 products

Intel® Programmable Devices

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