Article ID: 000085660 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I assign transceivers' REFCLK pin to a general purpose PLL in Stratix II GX and Stratix IV GX/GT devices?

Environment

    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You can assign transceivers' REFCLK pin as an input clock to a general purpose PLL in Stratix® II GX and Stratix IV GX/GT devices, only if you have instantiated at least one transceiver channel within the block associated with that REFCLK pin. You can instantiate a dummy transceiver channel to use this REFCLK pin and keep the dummy transceiver channel in reset state during normal operation.  

This information also applies to other GX/GT/GZ device families with dedicated high speed transceivers/REFCLK pins.

Related Products

This article applies to 13 products

Stratix® II GX FPGA
Stratix® IV GX FPGA
Arria® II GZ FPGA
Arria® II GX FPGA
Stratix® IV GT FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® GX FPGA
Arria® V SX SoC FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Stratix® GX FPGA

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