Article ID: 000085651 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why the pll_locked signal is always low in the SignalTap II file?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may observe the pll_locked signal to be always low in SignalTap® II tool, if you have selected an incorrect signal from the netlist.   When adding GXB transceiver lock signals into SignalTap II file, there are more than one choices: pll_locked[0] and pll_locked. pll_locked[0] node should be selected.  In hardware testing, pll_locked is always low.

 

pll_locked is a bus name, which should not be used in Signaltap II. You can confirm the connectivity in Quartus® II Analysis & Synthesis report.  In Analysis & Synthesis report file, there is a section called In-System Debugging.  This section shows the actual connections made by Quartus II software.  You will find that pll_locked is a missing node and connected to GND.  pll_locked[0] is a properly connected signal.

Related Products

This article applies to 4 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA
Arria® II GX FPGA
Cyclone® IV GX FPGA

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