Article ID: 000085641 Content Type: Troubleshooting Last Reviewed: 03/18/2013

Why are the Altera_PLL output clocks stuck low when simulating this megafunction in Cadence NCSim?

Environment

    Quartus® II Subscription Edition
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Description

If you are using NCSim to simulate the Altera_PLL megafunction, some of the output clocks may be stuck low.

Resolution

There are two workarounds for this issue:

1. To instantiate Altera_PLL, check "Enable physical output parameters" in the megafunction, and set the parameters accordingly to get the clocks you want.

2. Enable the macro SIM_USE_ICD_PLL_RECONFIG_MODEL to use the physical simulation model as shown below for Cyclone® V devices.  You will need to edit the commands below when targeting Arria® V or Stratix® V devices.

 ncvlog -DEFINE SIM_USE_ICD_PLL_RECONFIG_MODEL=TRUE "/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver

This issue is scheduled to be fixed in a future release of the Quartus® II software.

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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