Article ID: 000085627 Content Type: Error Messages Last Reviewed: 11/09/2011

Error in Getting Started Instructions for Post-Compilation Simulation

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The “Compile the Design in the Qsys Design Flow” section in the “Getting Started” chapter of the Stratix V Hard IP for PCI Express User Guide incorrectly instructs you to select ModelSim for the Simulation on the EDA Toll Settings page. This step causes the Quartus II software to try to create a post simulation netlist; however, post compilation netlist generation is not supported.

    This is a documentation error only.

    Resolution

    When creating your Quartus II project, do not select a simulation tool on the EDA Tool Settings page.

    This is fixed version 11.1 of the Stratix V Hard IP for PCI Express User Guide.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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