Article ID: 000085623 Content Type: Troubleshooting Last Reviewed: 10/09/2013

Synchronous edges BOTH requires associated clock

Environment

    Quartus® II Subscription Edition
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Description

You will get this error message if you generate a Qsys system that contains a PCIe® Hard IP core, the nreset_status signal is exported and a testbench is being generating.  This signal is intended to be used internally to the Qsys system and not exported for the testbench. 

Resolution

To use the nreset_status signal outside of the Qsys system for the testbench, generate the Qsys system without exporting the signal.  You can then bring out the nreset_status signal from the <instantiation name>.v file to the top level testbench of your design.  This can be done by editing the port declaration in the top level testbench file.  You will have to make this change each time you generate your Qsys system.

Note: the nreset_status signal is synchronous to the coreclkout clock signal. 

Related Products

This article applies to 13 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V SE SoC FPGA

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