Article ID: 000085623 Content Type: Troubleshooting Last Reviewed: 10/09/2013

Synchronous edges BOTH requires associated clock


  • Quartus® II Subscription Edition

    You will get this error message if you generate a Qsys system that contains a PCIe® Hard IP core, the nreset_status signal is exported and a testbench is being generating.  This signal is intended to be used internally to the Qsys system and not exported for the testbench. 


    To use the nreset_status signal outside of the Qsys system for the testbench, generate the Qsys system without exporting the signal.  You can then bring out the nreset_status signal from the <instantiation name>.v file to the top level testbench of your design.  This can be done by editing the port declaration in the top level testbench file.  You will have to make this change each time you generate your Qsys system.

    Note: the nreset_status signal is synchronous to the coreclkout clock signal. 

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