Article ID: 000085618 Content Type: Error Messages Last Reviewed: 08/27/2013

Critical Warning: PLL <PLL name> input clock inclk[0] is not fully compensated because it is fed by a remote clock pin <Pin Location>.

Environment

  • Quartus® II Subscription Edition
  • PLL
  • Clock
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might get this critical warning message in the Quartus® II software versions 10.0, 10.0sp1, 10.1, 10.1sp1, and  11.0 even when you feed a dedicated input clock pin to a PLL in Arria II GX devices.

    Refer to tables 5-6 or 5-7 in Clock Networks and PLLs in Arria II Devices (PDF) for accurate dedicated input clock pin to PLL mapping. The input path to the PLL will be fully compensated if the correct clock source is selected according to these tables.

    Resolution

    This critical warning message has been removed in the Quartus II software version 11.0sp1.

    Related Products

    This article applies to 3 products

    Arria® FPGAs
    Arria® II FPGAs
    Arria® II GX FPGA

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