How do I resolve recovery and removal timing violations associated with the global_reset_n pin of the Arria 10 EMIF IP ?

The Arria 10 EMIF IP global_reset_n signal can be driven from an asynchronous or synchronous source.

The global_reset_n signal is synchronized to the clock domains to generate synchronous reset signals inside the hard EMIF IP. Any removal and recovery timing violations associated with user signals driving the global_reset_n input port to nodes inside the EMIF IP can be cut.

Add a set_false_path constraint to your project with the following format:

set_false_path -from <reset signal connected to EMIF IP global_reset_n port> -to <EMIF IP instance_name>*

An example constraint is :

set_false_path -from clkrst|clkrst\|global_reset_n* -to packet:packet_i|packet_altera_emif_151*