Article ID: 000085607 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Why is the output voltage signal not monotonic at the rising and falling edges of the 1.8V SSTL 50 ohm On-Chip Termination (OCT) without calibration IBIS models in Cyclone III devices?

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Description

There is a known issue with the final Cyclone® III device IBIS models where the output voltage signal is not monotonic at the rising and falling edges of the 1.8V SSTL 50 ohm On-Chip Termination (OCT) without calibration. The corrected Cyclone III  IBIS models file can be downloaded from the link given below:

CIII_Corrected_IBIS_Model_2.ibs

The affected and corrected IBIS models are listed below:

- ttl18_cio_r50
- ttl18_cio_r25
- hstl18c1_cio_r50
- hstl18c2_cio_r25
- sstl18c1_cio_r50
- sstl18c2_cio_r25
- dhstl18c1_cio_r50
- dsstl18c1_cio_r50

Related Products

This article applies to 1 products

Cyclone® III FPGAs

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