Article ID: 000085599 Content Type: Troubleshooting Last Reviewed: 12/14/2012

Why does a change in the coefficient bit width change the compilation results in the Quartus II software?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This is a problem in the Quartus® II software when using the ALTMULT_ACC (MAC) Megacore with the pre-adder, and multiplier with coefficients. If the coefficients are set to 18 bits, which is the same as input, no additional resource will be used outside of the DSP Block. When the coefficient bit width is changed to 16 bits, the Chainin feature is not used within the DSP Block, and implimented in LEs.  

    Resolution

    If you are concerned with the additional logic outside of the DSP Block, keep the coefficient bit width to be 18-bits.

    This problem will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 1 products

    Arria® V GX FPGA

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