Article ID: 000085570 Content Type: Troubleshooting Last Reviewed: 08/14/2023

Why does the example design for the UniPHY-based memory controller have an Avalon-MM slave port as top-level I/O?

Environment

  • Quartus® II Subscription Edition
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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    Description

    UniPHY-based memory controllers with the On-chip Debug Toolkit enabled will have an Avalon®-MM slave port exported to the top level of the example design. The additional pins required by the Avalon-MM slave port could lead to "No Fit" errors for some smaller package sizes.

     

    Resolution

    To remove the Avalon-MM slave port, disable the On-chip Debug Toolkit and regenerate the example design, or manually remove the Avalon-MM slave port from the top level.

    This issue has been fixed in the Quartus® II software 13.1 version.

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