Article ID: 000085548 Content Type: Troubleshooting Last Reviewed: 02/21/2014

Why does my Cadence NCSim Cyclone V PCIe simulation fail to complete, getting stuck at L0?

Environment

    Quartus® II Subscription Edition
    Simulation
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to an issue when simulating the Cyclone® V Hard IP for PCI Express® using Cadence® NCSim®  the simulation models must be updated.
Resolution

To workaround this issue, please download these files UpdatedCycloneVModelFiles.zip and replace the existing files in location <your Quartus version>\quartus\eda\sim_lib\cadence

Related Products

This article applies to 6 products

Cyclone® V GT FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA

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