Article ID: 000085528 Content Type: Troubleshooting Last Reviewed: 02/20/2012

Altera QDR II Memory Model Behaves Differently Than Other Vendors’ Memory Models During Concurrent Transactions

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects QDR II products.

    During concurrent transactions where read and write commands to the same address occur on the same clock cycle, the expected preload value is overwritten by the concurrent write command.

    If you issue write–read–write commands to the same address with certain TCL-TCWL combination settings, the Altera memory model delivers the most recent information associated with the specified address location.

    Resolution

    There is no workaround for this issue.

    This issue will not be fixed.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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