Article ID: 000085526 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Does the Stratix® II have data rate restriction on high speed differential I/O channels for the 1508-pin package?

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Description Previous to version 3.1 of the Stratix® II Handbook volume 2 chapter 5 High-Speed Differential I/O Interfaces with DPA in Stratix II Devices stated channels more than 23 rows away from the center FPLLs (not including the reference clock row) could not operate at 1Gbps for devices offered in the 1508-pin package. However, Altera® performed further characterization and increased performance for slow speed channels to over 1Gbps(-3,-4)/840Mbps(-5).

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Stratix® II FPGAs

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