Due to a problem in the Quartus® Prime Standard edition software version 16.0 Update 2 and earlier, you may see this critical severity warning in the "Port Connectivity Checks" section of the Synthesis report for cases where there are no discontinuities between the connected expressions.
This warning may occur in error when connections are made between VHDL and Verilog HDL blocks.
View the stated connection in the RTL viewer to verify whether the connection has been made correctly.
This problem is scheduled to be fixed in a future release of the Quartus Prime Standard edition software.